| Time：1150610 (Wed.) 14:20~16:20 Speaker：Prof.葉昭輝(YEH, Chao-Hui) 國立清華大學電子工程研究所/Institute of Electronics Engineering, National Tsing Hua University Title：The Rise of 2D Electronics: From Fundamentals to Advanced Logic Applications Abstract： Since the groundbreaking isolation of monolayer graphene in 2004, research into van der Waals (vdW) layered crystals has surged, inspiring tremendous interest in a broader class of two-dimensional (2D) materials due to their intriguing physical and chemical properties, making them promising candidates for next-generation electronic technologies. Nowadays, the field of 2D electronics stands at the forefront of semiconductor research, potentially driving a paradigm shift toward high-performance, energy-efficient electronic devices.This presentation will provide a concise overview of four key thrusts in the development of 2D semiconductors (2DS) and their roles in advancing modern electronics: 1.Material fundamentals: The discussion begins with the synthesis of 2DS using low-temperature chemical vapor deposition (CVD) techniques, which enable integration into industrial-scale electronic applications. 2. Tailored Substitutional-Doping Technology in 2DS system: Tungsten diselenide (WSe2) has emerged as a promising candidate for advancing field-effect transistors (FETs), particularly for p-type operation. However, intrinsic WSe₂ typically exhibits ambipolar transport, making it difficult to achieve robust p-type doping and creating a bottleneck for energy-efficient complementary metal–oxide–semiconductor (CMOS) technology. This approach demonstrates a CVD-driven vanadium (V) doping strategy for WSe₂, enabling the controllable engineering of carriers and the stabilization of p-type conductivity. 3.2D-based Monolithic Transistor Integration: Leveraging wafer-scale CVD-MoS₂ as n-channel materials with transfer processes, we demonstrate enhancement-mode transistors with minimal off-currents under zero gate bias. To co-integrate MoS₂ n-FETs with well-established silicon-on-insulator (SOI) p-FinFETs in a vertically stacked common-gate complementary FET (CFET) architecture, sharing a single gate electrode across tiers to achieve the monolithic 3D hetero-ICs (M3D HICs). Using this platform, compact, energy-efficient gates and circuits, including inverters, NAND/NOR, XOR, ring oscillators (ROSC), and six-transistor static RAM (6T-SRAM) cells, can be established on a 2D/Si M3D logic platform for high-performance systems. 4.Memory-in-Logic with 2DS: Beyond logic, the monolithic device fabrication technology offers a promising route to adapt memory for data-intensive computing. To increase on-chip capacity with area-efficient demands, we utilize a heterogeneous CFET stack to implement embedded DRAM (eDRAM) at the logic tier. The eDRAM serves as a practical “knob” for multi-bit operation, supporting a compact, energy-efficient, high-performance memory-in-logic platform that will boost advancement in the AI era. In summary, 2D electronics represent a rapidly evolving and up-and-coming field poised to extend the trajectory of Moore’s Law. This presentation will outline the significant challenges, potential advantages, and future directions of 2D electronics, with the proposed M3D-HIC platform serving as a potential vanguard for innovative solutions in big data, AI-accelerated hardware, and high-performance logic applications (See the attached figure) Place：S101, Gongguan Campus, NTNU |
